Designing Hardware Abstraction for High-Performance Deep Learning Inference Accelerators

Hanjoon Kim

Speaker's bio

Hanjoon Kim is co-founder and CTO of FuriosaAI Inc. He is leading AI chip development, setting the engineering direction and technology vision.

Prior to FuriosaAI Inc, he lead the development of memory-centric accelerator architecture targeting hyperscale datacenter at Samsung Memory. He holds a PhD in Computer Science from KAIST.


Track : track3
Date: Day 2
Time: 14:50 ~ 15:20

Session detail

There has been extensive research into microarchitectures for efficiently accelerating deep learning, and numerous companies have developed deep learning accelerators with higher performance and energy efficiency than GPUs. However, GPUs are still predominantly used. Many deep learning accelerator products have shown high performance in some benchmark results, but they have failed to demonstrate competitive performance against GPUs for various models or have failed to run. The key reasons are that the design of the accelerator is not flexible enough to run a variety of models, or the programming model induces excessive software complexity, leading to failure in software optimization. In this talk, we will discuss the importance of hardware abstraction in reducing hardware and software complexity in the design of domain-specific accelerators, and aim to propose a direction for hardware abstraction suitable for high-performance deep learning inference accelerators.